From the state of the art, various methods for address assignment in Local Interconnect Network (LIN) bus systems are known. By way of example, reference should be made to the documents DE-B-10 2010 026 431, DE-B-10 147 512, EP-B-1 490 772 and U.S. Pat. No. 9,331,866.
All of these documents have in common that the number of bus nodes which are addressable by the bus master (hereunder referred to as addressable bus nodes) is limited because, in the framework of the auto addressing, each bus node will feed a defined current into the bus. In the one-wire data bus, each addressable bus node has shunt resistors (bus shunts) inserted into it where these currents, while on their way to the bus master—in which, during the address assignment process, a current sink is active—will cause a voltage drop. In the process, the addressable bus nodes arranged closest to the bus master will register a larger voltage drop than the addressable bus nodes arranged at a larger distance from the bus master. The voltage across the bus shunt is compared to a threshold value. If the latter is exceeded, the respective bus node at whose bus shunt this threshold violation takes place, is allowed to assume it is not the last bus node in the chain of the addressable bus nodes as viewed from the bus master. The bus node will then switch off its power source and wait for the next initialization run.
That addressable bus node which is the last bus node in the bus node chain as viewed from the bus master will not switch off its power source. After lapse of a predetermined initialization time, this bus node is allowed to assume it is the last addressable bus node to be addressed in the chain of the addressable bus nodes. It will then take over the bus node address transmitted by the bus master and will not participate in further initialization runs anymore until the received bus node address is declared to be invalid by a reset instruction or another reset condition.
The problem now is that, first, the electrical resistance of the bus shunt should be as small as possible. Second, the largest number possible of addressable bus nodes should be addressable. Third, the addressing system should be capable of working with a negative ground offset. Fourth, the level across the bus shunt has to be maximized, which requires a largest possible addressing current. Fifth, the summated current which has to be taken up by the bus master during the address assignment process is not permitted to exceed a predetermined value, in LIN busses presently 40 mA.
From DE-B-10 2010 026 431, a method is known wherein the individual addressable bus nodes do not work with a constant addressing current as in DE-B-10 147 512 and EP-B-1 490 772 but will increase this addressing current continuously or in a staircase-shaped manner until exceeding the thresholds at the preceding bus nodes. This has several disadvantages: First, in case that there exists a very large number of addressable bus nodes, this will lead to a temporally very long rising time. The time for performing the auto addressing, however, is limited. For this reason, it is necessary to shorten this time up to the addressing of the addressable bus node which is most remote from the bus master and has not been addressed yet. Thus, DE-B-10 2010 026 431 does not entirely solve the problem as to how to be able to address a very large number of addressable bus nodes and to sufficiently lower the resistance value of the bus shunt resistor. Further, the technical teaching disclosed in DE-B-10 2010 026 431 does not lead to a self-testing functionality.
A further disadvantage of DE-B-10 2010 026 431 resides in that, also here, for reasons of robustness, a certain level range has to be kept free in order to prevent the occurrence of overstress of the master or of faulty addressing. Thus, for minimizing the bus-shunt resistances and for establishing conformity with the LIN bus, it is reasonable to maximize the constant component in the addressing current. In the technical teaching disclosed in DE-B-10 2010 026 431, however, this value is varying around an addressing current value. Thereby, the available addressing current level is unnecessarily reduced.
From DE-B-10 256 631, EP-B-1 603 282, U.S. Pat. No. 7,590,140, EP-B-1 490 772 and EP-B-1 298 851, bus node addressing methods are known which require a shunt bus resistor (R2) within each auto-addressable bus node (SL1, SL2, SL3). This resistor has the disadvantage that it will degrade the EMC behavior toward a standard-conformal LIN bus node.